1. Field of the Invention
The present invention relates to an insulation structure. In particular, the present invention relates to a self-alignment insulation structure useful in the passing gates.
2. Description of the Prior Art
In the development of DRAM process, word lines are arranged to pass over other trench capacitors which are not controlled by this word line in order to increase the element density on the chip and enhance the integration effectively. FIG. 1 illustrates the word lines passing over other trench capacitors which are not controlled by this word line. As shown in FIG. 1, on the layout pattern, each word line 101 passes other adjacent non-active areas over the active area 102, the deep trench capacitors 103 and the shallow trench isolations (STI) . Before the deep trench capacitors 103 are actually formed, there are only the shallow trench isolations and the active area 102 in/on the substrate because any non-STI region is an active area. Such word lines that pass over the non-active areas and the deep trench capacitors are called “passing gates” because the gate elements are only formed on the overlapping regions of the word lines 101 and the active area 102.
A layer of an insulation structure must be constructed between the passing gates and the deep trench capacitors to ensure the electrical insulation between the passing gates and the deep trench capacitors because the passing gates and the deep trench capacitors both are electrical elements and the passing gates need to pass over the deep trench capacitors of other memory cells. As shown in FIG. 1, the insulation 105 in fact serves as the electrical insulation between the passing gates 104 and the deep trench capacitors 103. It should be noted that merely one insulation structure is shown on FIG. 1 and other incomplete insulation structures are omitted, which suggests other insulation structures may also exist on other deep trench capacitors.
Sequentially speaking, the shallow trench isolation is formed first, next the deep trench capacitors then the insulation structure of the passing gates are defined when the passing gates pass over the shallow trench isolation and the deep trench capacitors. FIGS. 2-8 illustrate the conventional steps to form the insulation structure of the passing gates. First, as shown in FIG. 2, the deep trench capacitor 203 is formed after the shallow trench isolation 202 is formed in the substrate 201. The steps to form the deep trench capacitor 203 may be that, the profile of the deep capacitor trench is first formed by etching, next the bottom of the capacitor trench is enlarged to form a bottle shape to pursue a larger inner surface, afterwards other elements such as the collar oxide is formed, then the capacitor trench is filled with a conductive material, such as silicon. After the deep trench capacitor 203 is formed, other necessary processes such as ion well (not shown) implantation, cleaning, or thermal annealing are performed. Secondly, as shown in FIG. 3 the pad oxide layer 204 and the silicon nitride layer 205 are sequentially formed on the substrate 201 to facilitate the formation of the photo-mask to define the location of the insulation structure. Afterwards, as shown in FIG. 4, the BARC layer 206 is formed and a patterned photoresist 207 is formed to define the location of the insulation structure for the passing gates. In the meantime, the photoresist 207 should precisely cover the shallow trench isolation 202 and the deep trench capacitor 203 to ensure the insulation structure for the passing gates is in the correct position.
Then, as shown in FIG. 5, part of the BARC layer 206 and the silicon nitride layer 205 are removed by etching. Next, as shown in FIG. 6, the remaining photoresist 207 and the BARC layer 206 are removed to leave the required silicon nitride layer 205 and the pad oxide layer 204. In the meantime the silicon nitride layer 205 serves as a hard mask. Thereafter, as shown in FIG. 7, the pad oxide layer 204 which is not masked by the silicon nitride layer 205 is removed by etching using the silicon nitride layer 205 as the hard mask. Afterwards, in FIG. 8, a gate oxide layer (not shown) is formed and the gate 210 is formed on the gate oxide layer and the passing gate 220 is formed on the silicon nitride layer 205 conventionally. Theoretically speaking, the passing gate 220 now is supposed to be formed on the deep trench capacitor 203. In other words, the silicon nitride layer 205 and the pad oxide layer 204 which are not removed in FIG. 7 now serve as the insulation structure 221 for the passing gate 220. The gate 210 is useful in controlling the deep trench capacitor 203 to form a memory cell. This way, the insulation structure 221 ensures that an excellent insulation is established between the passing gate 220 and the underlying, deep trench capacitor 203 to avoid shorts and to avoid interfering with the performance of the DRAM.
However, the above-mentioned procedure not only requires an additional mask to define the position of the insulation structure 221, moreover it is extremely difficult to define the insulation structure 221, i.e. the pad oxide layer 204 and the silicon nitride layer 205, above the deep trench capacitor 203 with little misalignment. Furthermore, there is no sufficient protection to keep the exposed shallow trench isolation 202 and the deep trench capacitor 203 from the possible damages resulting from the ion well implantation, cleaning, or thermal annealing before the completion of the insulation structure 221.
Therefore, a novel method for forming an insulation structure is needed to eliminate an additional mask to define the position of the insulation structure, to get rid of the misalignment between the insulation structure and the previously-established deep trench capacitor, and further to protect the substrate, the shallow trench isolation and the deep trench capacitor from exposure and from the collateral damages brought about by the formation of other regions before the completion of the insulation structure.